VHDL BEHAVIORAL MODEL

  • Shivangi Shandilya College Of Engineering , Gurgaon
  • Surekha Sangwan College Of Engineering , Gurgaon
  • Ritu Yadav College Of Engineering , Gurgaon
Keywords: VHDL, BEHAVIORAL, MODEL

Abstract

The language constructs introduced so far allow hardware to be described at a relatively detailed level. Modeling a circuit with logic gates and continuous assignments reflects quite closely the logic structure of the circuit being modeled; however, these constructs do not provide the power of abstraction necessary for describing complex high level facets of a system. The procedural constructs described in this chapter are well suited to tackling problems such as describing a microprocessor or implementing complex timing checks. With the increasing complicacy of digital design, it has become vitally important to make wise design decisions early in a project. Designers need to be able to evaluate the trade-off of various architectures and algorithms before they decide on the optimum architecture and algorithm to device in hardware

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Author Biographies

Shivangi Shandilya, College Of Engineering , Gurgaon

Dept. of Computer Science Engineering

Surekha Sangwan, College Of Engineering , Gurgaon

Dept. of Computer Science Engineering

Ritu Yadav, College Of Engineering , Gurgaon

Dept. of Computer Science Engineering

Published
2015-04-30
How to Cite
Shandilya, S., Sangwan, S., & Yadav, R. (2015). VHDL BEHAVIORAL MODEL. IJRDO -Journal of Computer Science Engineering, 1(4), 05-08. https://doi.org/10.53555/cse.v1i4.489