Design and analysis of Compressor Based Area-Efficient, High-speed Low-Power Multiplier
Abstract
Multiplication is the basic arithmetic operation that is important in several microprocessors and digital signal-processing applications. Microprocessors use multipliers within their arithmetic logic units, and digital signal processing systems require multipliers to implement DSP algorithms such as convolution and filtering. Multipliers being the most area and power-consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, a multiplier based on an ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3, and 7:3 compressors for the addition of partial products. Combining the Vedic multiplier and efficient compressors, a robust area and power-efficient multiplier architecture has been achieved. The designs were synthesized and analyzed in Cadence Virtuoso in 180 nm technology. When compared with the previous compressor-based multiplier, the proposed design achieves a reduction in power and area respectively.
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References
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